1. Field of the Invention
Embodiments of the invention relate to semiconductor integrated circuits and semiconductor physical quantity sensor devices.
2. Related Art
To date, a laser trimming method has been commonly known as a method of regulating the output characteristics of a physical quantity sensor. The heretofore known laser trimming method has a drawback in that, even in the event that fluctuation occurs in the physical quantity sensor output characteristics in an assembly step after trimming, re-regulation is not possible.
Because of this, in recent years, an electrical trimming method, whereby the physical quantity sensor output characteristics can be regulated after the finish of the assembly step, has been used. With electrical trimming, however, a large number of control terminals are necessary for inputting and outputting trimming data, writing data into an EPROM, and the like. Because of this, there is a problem in that manufacturing cost increases due to factors such as the number of wire bondings increasing.
Therefore, a device wherein the number of terminals is reduced by providing a plurality of terminal action threshold voltages using resistive voltage division and a bipolar transistor, and electrical trimming is carried out with a small number of terminals, has been proposed as a device that eliminates this kind of problem (for example, refer to Japanese patent document no. JP-A-6-29555 (“JP-A-6-29555”)).
Also, a device that uses an EPROM as a storage device, wherein the number of terminals is reduced by one of one or two writing terminals supplying voltage for writing data into a storage circuit including the EPROM doubling as an external clock input terminal, has been proposed as another device (for example, refer to Japanese patent document no. JP-A-2003-302301 (“JP-A-2003-302301”)).
Also, it is proposed in JP-A-2003-302301 that a further two writing terminals are commonized, thus reducing the number of terminals, by providing a voltage conversion circuit that converts writing voltage supplied from an EPROM writing terminal, thereby generating a different writing voltage. Also, with regard to JP-A-2003-302301, wherein a semiconductor physical quantity sensor device can be manufactured by a CMOS process, the external clock input terminal (5.0V or less) and a writing terminal that needs a high voltage (in the region of 20V) are commonized. Further, using a signal distinguishing means (circuit), it is determined from the size of an input voltage whether the voltage is a writing voltage to the storage circuit or an external clock.
Because of this, when applying JP-A-2003-302301, it is necessary that the signal distinguishing means circuit is configured of a CMOS element, or the like, with a high breakdown voltage. Also, a stabilizing power source circuit that can generate a stable output voltage, without being affected by variation in output transistor characteristics even in the event that a load current in a load with low voltage and low power consumption is of a low value such as to respond to element leakage current, has been proposed as a circuit that generates output voltage (for example, refer to Japanese patent document no. JP-A-2000-194431 (“JP-A-2000-194431”)).
Also, a power source circuit that, as it uses a CMOS type transistor wherein circuit current is limited by a resistor inserted between a back gate and a source and thus does not increase to a predetermined value or above, prevents dielectric breakdown even in a short-circuit condition has been proposed as another circuit (for example, refer to Japanese Patent No. 3,068,540 (“3,068,540”)).
Also, a power source circuit configured to include in one portion a step-up switching power source circuit has been proposed as another circuit (for example, refer to Japanese Patent No. 3,480,389 (“3,480,389”)). Also, an internal voltage generating circuit such that, even in the event that there is a temporary drop in the outputs of the internal voltage generating circuit and a constant potential generating circuit with small circuit areas, wherein there are a large number of correction points and a highly accurate output voltage is obtained, the internal voltage can reliably be generated again has been proposed as another circuit (for example, refer to Japanese patent document no. JP-A-2001-242949 (“JP-A-2001-242949”)).
Also, a device wherein a voltage supply circuit has a power source step-up unit, an amplifier that acts with voltage generated by the power source step-up unit as power source voltage and supplies bias voltage to a sensor, and an output voltage setting circuit having a feedback resistor unit for the amplifier, wherein the resistance value of the feedback resistor unit is determined in accordance with the setting value of the sensor bias voltage, has been proposed as another circuit (for example, refer to Japanese patent document no. JP-A-2006-191359 (“JP-A-2006-191359”)). In JP-A-2006-191359, when sensitivity of each of sensor apparatuses, for example, condenser mic units, varies, it is possible to adjust the sensitivity.
However, in JP-A-2003-302301, no specific circuit example is disclosed for the voltage conversion circuit that converts writing voltage supplied from the writing terminal, thereby generating a different writing voltage. FIG. 10 is a block diagram showing a configuration of a heretofore known semiconductor physical quantity sensor device. FIG. 10 is a semiconductor physical quantity sensor device with an EPROM as a main memory circuit, and corresponds to FIG. 10 of JP-A-2003-302301. A voltage conversion circuit 18a, corresponding to a voltage conversion circuit indicated by reference sign 118 in FIG. 10 of JP-A-2003-302301, generates a writing voltage 2 by converting a writing voltage 1, but no specific circuit diagram of the voltage conversion circuit 18a is shown in JP-A-2003-302301. Also, in FIG. 10 of JP-A-2003-302301, a transmission line of the writing voltage 1 and writing voltage 2 is shown by one arrow.
The semiconductor physical quantity sensor device 5 includes an action selection circuit 11, an auxiliary memory circuit 12, a main memory circuit 13, a regulation circuit 14, a sensor element 15, such as a Wheatstone bridge, an amplifier circuit 16, a signal distinguishing means 17, the voltage conversion circuit 18a, and five terminals 21 to 25, from a first to a fifth. Also, in JP-A-2003-302301, no specific circuit example is disclosed for the auxiliary memory circuit 12 and main memory circuit 13 either.
To write data into the unshown EPROM configuring the main memory circuit 13, firstly, a voltage (a writing voltage 2) of in the region of 10V is applied between the source and drain in a condition in which a voltage (a writing voltage 1) of in the region of 20V is applied to the control gate. Then, current is caused to flow between the source and drain, and it is necessary for a charge to be trapped in the floating gate by an electrical field generated between the drain and gate.
In general, when writing into an EPROM, it is preferable that the writing voltage and number of writes are of constant values in order to prevent damage to the element when writing and to keep the amount of charge injected into the control gate practically constant (to keep the writing voltage constant). Therefore, it is necessary that the writing voltage 1 and writing voltage 2 are kept constant.
Also, it is common that writing into an EPROM is not carried out one bit at a time, but is carried out for all bits simultaneously, or for a number of blocks at a time. When writing into all bits simultaneously, or into the EPROMs in a certain block simultaneously, a switch is provided between the drain of each EPROM and the writing voltage 2. Then, the switches of bits to be written into are turned on, so that a current flows between the source and drain. Meanwhile, the switches of bits not to be written into are turned off, so that no current flows between the source and drain.
The ratio between the bits to be written into and bits not to be written into within the block differs in accordance with a regulation value (trimming conditions). Because of this, the number of EPROMs through which current flows simultaneously for one write is not constant. Therefore, for example, when forming the writing voltage 2 from the writing voltage 1 using resistive division (voltage division), the load (resistance value) changes in accordance with the number of EPROMs through which current flows. Further, as the combined resistance of this and the resistance used for the resistive division changes, it is not possible to keep the writing voltage 2 constant.
To keep the writing voltage 2 constant, it is necessary that the load dependency of the voltage conversion circuit 18a is low when forming the writing voltage 2 from the writing voltage 1. That is, it is necessary to arrange that the voltage conversion circuit 18a does not depend on the number of EPROMs configuring the main memory circuit 13 that have continuity.
Also, in JP-A-2000-194431, 3,068,540 and 3,480,389, there is no description of the power source circuit being applied to a semiconductor physical quantity sensor device. Also, in JP-A-2001-242949 and JP-A-2006-191359, a description is given of a power source circuit wherein the output voltage is changed by changing the resistance value of the resistive voltage dividing circuit, but there is no description of using the output voltage (writing voltage 2) as a writing voltage for a plurality of EPROMs.
Also, in JP-A-6-29555, a bipolar transistor and an EPROM fabricated by a CMOS process exist together, meaning that a BiCMOS process is necessary. Because of this, there is a problem in that there are more steps than with only a CMOS process, leading to an increase in cost. Also, in the case of JP-A-2003-302301, manufacture is possible with only a CMOS process, but as it is necessary to configure the signal distinguishing means circuit with a high breakdown voltage CMOS element or the like, there is a problem in that the element size increases, and thus the circuit area increases.
Also, when providing an ESD (Electro-Static Discharge) protection element such as a ZD (Zener Diode) in a high-voltage terminal such as a writing terminal, it is necessary to connect a plurality of ZDs in series, and there is a problem in that the area of the protection element is larger than that in a low-voltage signal terminal.
Also, even when a high-voltage terminal and low-voltage terminal are commonized, the same protection element as for a high-voltage terminal is necessary for the commonized terminals, meaning that an area reduction advantage is such that it is only possible to reduce the area by an amount equivalent to the protection element of the low-voltage terminal with the smaller area. Consequently, in JP-A-2003-302301, there is a problem in that the area reduction advantage from the commonizing of terminals is small due to the increase in area caused by the addition of the high breakdown voltage signal distinguishing circuit, and it is not possible to expect a significant reduction in cost. Thus, as is described above, there is a need in the art for an improved semiconductor integrated circuit and semiconductor physical quantity sensor device.